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HM65W8512 series 4 m psram (512-kword 8-bit) 2 k refresh ade-203-289c(z) rev. 3.0 nov. 1997 description the hitachi HM65W8512 is a cmos pseudo static ram organized 512-kword 8bit. it realizes higher density, higher performance and low power consumption by employing 0.8 m m hi-cmos process technology. it offers low power data retention by self refresh mode. it also offers easy non multiplexed address interface and easy refresh functions. HM65W8512 is suitable for handy systems which work with battery back-up systems. the device is packaged in a small 525-mil sop (460-mil body sop) or a 400 mil tsop type ii. features single 3.3 v ( 0.3v) high speed ? access time ce access time: 120/150 ns (max) ? cycle time random read/write cycle time: 190/230 ns (min) low power ? active: 100 mw (typ) ? standby: 85 m w (typ) directly ttl/cmos compatible all inputs and outputs simple address configuration non multiplexed address refresh cycle ? 2048 refresh cycles: 32 ms
HM65W8512 series 2 easy refresh functions address refresh automatic refresh self refresh ordering information type no. access time package HM65W8512lfp-12 HM65W8512lfp-15 120 ns 150 ns 525-mil 32-pin plastic sop (fp-32d) HM65W8512lfp-12v HM65W8512lfp-15v 120 ns 150 ns HM65W8512ltt-12 HM65W8512ltt-15 120 ns 150 ns 400-mil 32-pin plastic tsop (ttp-32d) HM65W8512ltt-12v HM65W8512ltt-15v 120 ns 150 ns HM65W8512lrr-12 HM65W8512lrr-15 120 ns 150 ns 400-mil 32-pin plastic tsop (ttp-32dr) HM65W8512lrr-12 HM65W8512lrr-15v 120 ns 150 ns
HM65W8512 series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v a15 a17 we a13 a8 a9 a11 oe/rfsh a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 cc HM65W8512fp series (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ss v a15 a17 we a13 a8 a9 a11 oe/rfsh a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v cc HM65W8512tt series (top view)
HM65W8512 series 4 pin arrangement (cont.) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ss v a15 a17 we a13 a8 a9 a11 oe/rfsh a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v cc HM65W8512rr series (top view) pin description pin name function a0 to a18 address i/o0 to i/o7 input/ output ce chip enable oe / rfsh output enable/refresh we write enable v cc power supply v ss ground
HM65W8512 series 5 block diagram refresh control timing pulse gen. read write control address latch control column decoder column i/o memory matrix row decoder address latch control input data control ce we i/o 7 i/o 0 a0 a10 a11 a18 oe/rfsh (2048 256) 8 pin functions ce : chip enable (input) ce is a basic clock. ram is active when ce is low, and is on standby when ce is high. a0 to a18: address inputs (input) a0 to a10 are row addresses and a11 to a18 are column addresses. the entire addresses a0 to a18 are fetched into ram by the falling edge of ce . oe / rfsh : output enable/refresh (input) this pin has two functions. basically it works as oe when ce is low, and as rfsh when ce is high (in standby mode). after a read or write cycle finishes, refresh does not start if ce goes high while oe / rfsh is held low. in order to start a refresh in standby mode, oe / rfsh must go high to reset the refresh circuits of the ram. after the refresh circuits are reset, the refresh starts when oe / rfsh goes low. i/o0 to i/o7: input/output (inputs and outputs) these pins are data i/o pins.
HM65W8512 series 6 we : write enable (input) ram is in write mode when we is low, and is in read mode when we is high. i/o data is fetched into ram by the rising edge of we or ce (earlier timing) and the data is written into memory cells. refresh there are three refresh modes : address refresh, automatic refresh and self refresh. (1) address refresh: data is refreshed by accessing all 2048 row addresses every 32 ms. a read is one method of accessing those addresses. each row address (2048 addresses of a0 to a10) must be read at least once every 32 ms. in address refresh mode, oe / rfsh can remain high. in this case, the i/o pins remain at high impedance, but the refresh is done within ram. (2) automatic refresh: instead of address refresh, automatic refresh can be used. ram goes to automatic refresh mode if oe / rfsh falls while ce is high and it remains low for at least t fap . one automatic refresh cycle is executed by one low pulse of oe / rfsh . it is not necessary to input the refresh address from outside since it is generated internally by an on-chip address counter. 2048 automatic refresh cycles must be done every 32 ms. (3) self refresh: self refresh mode is suitable for data retention by battery. in standby mode, a self refresh starts automatically when oe / rfsh stays low for more than 8 m s. refresh addresses are automatically specified by the on-chip address counter, and the refresh period is determined by the on-chip timer. automatic refresh and self refresh are distinguished from each other by the width of the oe / rfsh low pulse in standby mode. if the oe / rfsh low pulse is wider than 8 m s, ram becomes into self refresh mode; if the oe / rfsh low pulse is less than 8 m s, it is recognized as an automatic refresh instruction. at the end of self refresh, refresh reset time (t rfs ) is required to reset the internal self refresh operation of the ram. during t rfs , ce and oe / rfsh must be kept high. if auto refresh follows self refresh, low transition of oe / rfsh at the beginning of automatic refresh must not occur during t rfs period. notes on using the HM65W8512 since pseudo static ram consists of dynamic circuits like dram, its clock pins are more noise-sensitive than conventional sram?. (1) if a short ce pulse of a width less than t ce min is applied to ram, an incomplete read occurs and stored data may be destroyed. make sure that ce low pulses of less than t ce min are inhibited. note that a 10 ns ce low pulse may sometimes occur owing to the gate delay on the board if the ce signal is generated by the decoding of higher address signals on the board. avoid these short pulses. (2) oe / rfsh works as refresh control in standby mode. a short oe / rfsh low pulse may cause an incomplete refresh that will destroy data. make sure that oe / rfsh low pulse of less than t fap min are also inhibited. (3) t ohc and t ocd are the timing specs which distinguish the oe function of oe / rfsh from the rfsh function. the t ohc and t ocd specs must be strictly maintained.
HM65W8512 series 7 (4) start the HM65W8512 operating by executing at least eight initial cycles (dummy cycles) at least 100 m s after the power voltage reaches 3.0 v-3.6 v after power-on. function table ce oe / rfsh we i/o pin mode l l h dout read l x l high-z write l h h high-z h l x high-z refresh h h x high-z standby note: x means h or l. absolute maximum ratings parameter symbol value unit terminal voltage with respect to v ss v t ?.5 to +6.0 v power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg ?5 to +125 c storage temperature under bias tbias ?0 to +85 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit note supply voltage v cc 3.0 3.3 3.6 v v ss 000 v input voltage v ih 2.4 5.6 v v il ?.5 0.8 v 1 note: 1. v il min = ?.2 v for pulse width 30 ns
HM65W8512 series 8 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) parameter symbol min typ max unit test conditions operating power supply current i cc1 ?050mai i/o = 0 ma t cyc = min standby power supply current i sb1 0.8 ma ce = v ih , vin 3 0 v oe / rfsh = v ih i sb2 ?530 m a ce 3 v cc ?0.2 v, vin 3 0 v, oe / rfsh 3 v cc ?0.2 v operating power supply current in self refresh mode i cc2 0.8 ma ce = v ih , vin 3 0 v, oe / rfsh = v il i cc3 ?550 m a ce 3 v cc ?0.2 v, vin 3 0 v, oe / rfsh 0.2 v input leakage current i li ? 5 m av cc = 3.6 v, vin = v ss to v cc output leakage current i lo ? 5 m a oe / rfsh = v ih v i/o = v ss to v cc output voltage v ol 0.1 v i ol = 100 m a 0.4 v i ol = 2 ma v oh 2.9 v i oh = ?00 m a 2.4 v i oh = ? ma capacitance (ta = 25 c, f = 1 mhz) parameter symbol typ max unit test conditions input capacitance* 1 c in 8 pf v in = 0 v input /output capacitance* 1 c i/o ?0 pfv i/o = 0 v note : this parameter is sampled and not 100% tested.
HM65W8512 series 9 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, unless otherwise noted.) test conditions input pulse levels: 0.6 v, 2.4 v input rise and fall time: 5 ns timing measurement level: 1.5 v reference levels: v oh = 2.1 v, v ol = 0.9 v output load: c l (50 pf) (including scope and jig) HM65W8512-12 HM65W8512-15 parameter symbol min max min max unit notes random read or write cycle time t rc 190 230 ns chip enable access time t cea 120 150 ns read-modify- write cycle time t rwc 250 290 ns output enable access time t oea 60 80 ns chip disable to output in high-z t chz 0 30 0 30 ns 1, 2 chip enable to output in low-z t clz 20 20 ns 2 output disable to output in high-z t ohz 30 30 ns 1, 2 output enable to output in low-z t olz 00ns2 chip enable pulse width t ce 120 10000 150 10000 ns chip enable precharge time t p 70 80 ns address setup time t as 00ns address hold time t ah 30 30 ns read command setup time t rcs 00ns read command hold time t rch 00ns write command pulse width t wp 35 35 ns chip enable to end of write t cw 120 150 ns chip enable to output enable delay time t ocd 00ns output enable hold time t ohc 15 15 ns
HM65W8512 series 10 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, unless otherwise noted.) (cont.) HM65W8512-12 HM65W8512-15 parameter symbol min max min max unit notes data in to end of write t dw 30 30 ns data in hold time for write t dh 00ns output active from end of write t ow 55ns2 write to output in high-z t whz 30 30 ns 1, 2 transition time (rise and fall) t t 3 50 3 50 ns 6 refresh command delay time t rfd 70 80 ns refresh precharge time t fp 40 40 ns refresh command pulse width for automatic refresh t fap 80 8000 80 8000 ns automatic refresh cycle time t fc 190 230 ns refresh command pulse width for self refresh t fas 88 m s refresh reset time from self refresh t rfs 600 600 ns 9 refresh period t ref 32 32 ms 2048 cycle notes: 1. t chz , t ohz , t whz are defined as the time at which the output achieves the open circuit condition. 2. t chz , t clz , t ohz , t olz , t whz and t ow are sampled under the condition of t t = 5 ns and not 100% tested. 3. a write occurs during the overlap of low ce and low we . write end is defined at the earlier of we going high or ce going high. 4. if the ce low transition occurs simultaneously with or from the we low transition, the output buffers remain in high impedance state. 5. in write cycle, oe or we must disable output buffers prior to applying data to the device and at the end of write cycle data inputs must be floated prior to oe or we turning on output buffers. during this period, i/o pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. transition time t t is measured between v ih (min) and v il (max). v ih (min) and v il (max) are reference levels for measuring timing of input signals. 7. after power-up, pause for more than 100 m s and execute at least 8 initialization cycles. 8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed within 15 m s after self refresh, in order to meet the refresh specification of 32 ms and 2048 cycles. 9. at the end of self refresh, refresh reset time (t rfs ) is required to reset the internal self refresh operation of the ram. during t rfs , ce and oe / rfsh must be kept high. if automatic refresh follows self refresh, low transition of oe / rfsh at the beginning of automatic refresh must not occur during t rfs period.
HM65W8512 series 11 timing waveform read cycle t ce address a0 to a18 we oe/rfsh t t tt valid t t t t dout t valid data out t t t rc ce as ah p rch chz ohz oea cea ohc rcs olz
HM65W8512 series 12 write cycle (1) ( oe high) ce address a0 to a18 we oe/rfsh din t t t tt valid dout valid data in t t tt t t t t t t rc ce as ah cw clz ohz whz wp ocd p dw dh olz ow
HM65W8512 series 13 write cycle (2) ( oe low) ce address a0 to a18 we oe/rfsh din t t t tt valid dout valid data in t t t t t t t rc ce p dh cw t wp dh dw whz clz ohc ah as
HM65W8512 series 14 read-modify-write cycle ce address a0 to a18 we oe/rfsh din t t t tt valid dout valid data in t t t t t t t t t valid data out t t t t t t rwc ce cw p rch ocd wp dh dw chz ow as ah rcs cea ohc oea olz clz ohz automatic refresh cycle ce oe/rfsh tt t tt tt rfd fc fp fap fp fap fc
HM65W8512 series 15 self refresh cycle ce oe/rfsh t t t t rfd fp fas rfs
HM65W8512 series 16 low v cc data retention characteristics (ta = 0 to +70 c) this characteristics is guaranteed only for v-version. parameter symbol min typ max unit test conditions v cc for data retention v dr 2.0 3.6 v self refresh current i ccdr 25 m av cc = 2.0 v, ce 3 v cc ?0.2 v oe / rfsh 0.2 vin 3 0 v 50 m av cc = 3.6 v, ce 3 v cc ?0.2 v oe / rfsh 0.2 vin 3 0 v refresh setup time t fs 0 ns operation recovery time t fr 5 ms low v cc data retention timing waveform data retention mode dr fas fs fr rfs t fp 3.0v 1.5v 1.5v v ce oe/rfsh ce vcc-0.2v oe/rfsh 0.2v cc rfd t tt t t (in read/ v f t r t write mode) (in automatic refresh mode)
HM65W8512 series 17 package dimensions HM65W8512fp series (fp-32d) unit: mm 0.15 0 ?8 m + 0.10 ?0.05 0.40 20.45 1.0 max 1.27 11.7 max 1.42 0.8 3.0 max 0.05 min 0.22 + 0.13 ?0.07 20.95 max 32 17 1 16 14.14 ?0.30 0.10 HM65W8512tt series (ttp-32d) unit: mm 1.27 0.21 m 0.40 0.10 0.10 10.16 20.95 21.35 max 17 16 32 1 1.20 max 0 ?5 0.08 min 0.18 max 0.17 0.05 11.76 0.2 0.50 0.10 1.15 max
HM65W8512 series 18 package dimensions (cont.) HM65W8512rr series (ttp-32dr) unit: mm 1.27 0.21 m 0.40 ?0.10 0.10 10.16 20.95 21.35 max 16 17 1 32 1.20 max 0 ?5 0.08 min 0.18 max 0.17 ?0.05 11.76 ?0.2 0.50 ?0.10 1.15 max
HM65W8512 series 19 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachi? permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user? unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi? semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachi? products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi? sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachi? products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071
HM65W8512 series 20 revision record rev. date contents of modification drawn by approved by 3.0 nov. 1997 change of subtitle

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